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Title  | Author(s) | Year | Where |
| A Polymorphic Register File Architecture | CB Ciobanu, G.K. Kuzmanov, A. Ramirez, G. N. Gaydadjiev | 2009 | Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), pp. 245-248, Terrassa, Spain, July 2009 |
| A Scalable and Early Congestion Management Mechanism for MINs | oan-Lluís Ferrer, Elvira Baydal, Antonio Robles, Pedro López, José Duato | 2010 | 18th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP 2010) |
| Instruction-Level Fault Tolerance Configurability | D. Borodin, B.H.H. Juurlink, S. Hamdioui, S. Vassiliadis | 2008 | Journal of Signal Processing Systems |
| Joint Compiler/Hardware Exploration for Fair Comparison of Architectures | Desmet, V.; Girbal, S.; Temam, O. | 2009 | Proceedings of the 13th Workshop on Interaction between Compilers and Computer Architecture |
| Proposition for a sequential accelerator in future general-purpose manycore processors | P. MICHAUD, Y. SAZEIDES, A. SEZNEC. | 2010 | International Conference on Computing Frontiers |
| Re-Nuca: Boosting CMP performances through block replication | P. Foglia, M. Solinas et al: | 2010 | 13th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD2010), September 1-3, Lille, France |
| (When) Will CMPs hit the Power Wall? | C.H. Meenderinck, and B.H.H. Juurlink | 2008 | Highly Parallel Processing on a Chip (HPPC) |
| (When) Will CMPs hit the Power Wall? | C.H. Meenderinck and B.H.H. Juurlink | 2008 | Technical Report |
| (When) Will CMPs hit the Power Wall? | C.H. Meenderinck and B.H.H. Juurlink | 2007 | Workshop on Circuits, Systems and Signal Processing (ProRISC) |
| . Schemes for Avoiding Starvation in Transactional Memory Protocols | M. M. Waliullah and P. Stenstrom | 2009 | Journal of Concurrency and Computation: Practice and Experience, Vol 21, No 7, pp. 859-873, 2009 |
| A 128x128x24Gb/s Crossbar, Interconnecting 128 tiles in a single hop, and Occupying 6% of their area | G. Passas, M. Katevenis, D. Pnevmatikatos | 2010 | 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2010) |
| A Chip MultiProcessor Accelerator for Video Decoding | C.H. Meenderinck, B.H.H. Juurlink | 2008 | Workshop on Circuits, Systems and Signal Processing (Prorisc) |
| A CMP L2 NUCA Cache Power Reduction Technique | Pierfrancesco Foglia, Francesco Panicucci, Cosimo A. Prete, Marco Solinas | 2008 | IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XI), pp 137-137, Yokohama, Japan, vol. 1 |
| A deterministic, concurrent intermediate representation for portable and scalable performance | C. Miranda, P. Dumont, A. Cohen, M. Duranton, and A. Pop. Erbium | 2010 | ACM Intl. Conf. on Computing Frontiers (CF10), May 2010. 2 pages and poster |
| A Highly Scalable Parallel Implementation of H.264 | Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink, Andrei Tereckho, Jan Hoogerbrugge, Mauricio Álvarez, Alex Ramirez and Mateo Valero | 2009 | Transactions on High-Performance Embedded Architectures and Compilers, vol. 4, no. 2, Sep 2009. |
