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Scalable computer ARChitecture
 
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Title Author(s) Year Where 
Reducing Sensitivity to NoC Latency in NUCA CachesPierfrancesco Foglia, Giacomo Gabrielli, Francesco Panicucci, Marco Solinas20093rd Workshop on Interconnection Network Architectures: On-Chip,Multi-Chip (INA-OCMC 2009)
The Design of OpenMP TasksEduard Ayguadé, Nawal Copty, Alejandro Duran, Jay Hoeflinger, Yuan Lin, Federico Massaioli, Xavier Teruel, Priya Unnikrishnan, and Guansong Zhang2009IEEE Transactions on Parallel and Distributed Systems, vol. 20, no.3, pp 404-418, March 2009
Stream Chaining: Exploiting Multiple Levels of Correlation in Data PrefetchingPedro Diaz and Marcelo Cintra2009Proceedings of the International Symposium on Computer Architecture
Exploiting DMA mechanisms to enable non-blocking execution in Decoupled Threaded ArchitectureR. Giorgi, Z. Popovic, N. Puzovic2009Proc. IEEE Workshop on Multithreaded Architectures and Applications, ISBN 978-1-4244-3751-1, Rome, Italy, May 2009, pp. 1 - 8
Implementing fine/medium grained tlp support in a many-core architectureR. Giorgi, Z. Popovic, N. Puzovic2009Proceedings of 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2009, ISBN 978-3-642-03137-3, Samos, Greece, jul 2009. pp. 78-87
Implementing finne/medium grained TLP support in multi-core architecturesNikola Puzovic2009PhD thesis, University of Siena, September 2009. ISBN 978-86-912901-0-8
Multithreaded Dataflow in Tiled ArchitecturesZdravko Popovic2009PhD thesis, University of Siena, September 2009. ISBN 987-86-912903-0-6
Instruction Precomputation for Fault DetectionD. Borodin and B.H.H. (Ben) Juurlink2009DSD-2009: 12th Euromicro Conference on Digital System Design
A Proposal to Extend the OpenMP Tasking Model with Dependent TasksAlejandro Duran, Roger Ferrer, Eduard Ayguadé, Rosa M. Badia and Jesus Labarta2009International Journal of Parallel Programming,Volume 37, Number 3, pp. 292-305, Springer Netherlands. 0885-7458 (Print) 1573-7640 (Online), April 25, 2009
A Proposal to Extend the OpenMP Tasking Model for Heterogeneous ArchitecturesEduard Ayguade, Rosa M. Badia, Daniel Cabrera, Alejandro Duran, Marc Gonzalez, Francisco Igual, Daniel Jimenez, Jesus Labarta, Xavier Martorell, Rafael Mayo, Josep M. Perez and Enrique S.Quintana-Ortí2009Lecture Notes in Computer Science, Book Evolving OpenMP in an Age of Extreme Parallelism, Volume 5568/2009, pp. 154-167, Springer Berlin / Heidelberg, ISSN 0302-9743 (Print) 1611-3349 (Online)
Available task-level parallelism on the Cell BEAlejandro Rico, Alex Ramirez and Mateo Valero2009Scientific Programming, vol. 17, no 1-2, pp. 59-76, ISSN:1058-9244, Feb 2009.
FlexDCP: a QoS framework for CMP architecturesMiquel Moretó, Francisco J. Cazorla, Alex Ramirez, Rizos Sakellariou and Mateo Valero2009ACM SIGOPS Operating Systems Review, pp. 86-96, vol. 43, no. 2, ISSN:0163-5980, Apr 2009.
Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor ArchitectureMauricio Álvarez, Alex Ramirez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck and Ben Juurlink20094th Colombian Computing Conference, Bucaramanga (Colombia), Apr 2009.
Exploiting Different Levels of Parallelism in the Biological Sequence Comparison ProblemFriman Sánchez, Alex Ramirez and Mateo Valero20094th Colombian Computing Conference, Bucaramanga (Colombia), Apr 2009.
Quantitative analysis of sequence alignment applications on multiprocessor architecturesFriman Sánchez, Alex Ramirez and Mateo Valero20096th ACM conference on Computing frontiers, pp. 61-70, 978-1-60558-413-3, Ischia (Italy), May 2009.
   
Publications found: 228Previous pageNext page
   

 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants



IST-FET project funded under the 6th Framework Programme


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