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Scalable computer ARChitecture
SARC Project
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Title Author(s) Year Where arrow
Impact of On-Chip Network Parameters on NUCA Cache PerformanceA. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete2009 IET Computers & Digital Techniques, Vol. 3, No. 5, pp. 501-512, August 2009
Polyhedral-model guided loop-nest auto-vectorizationK. Trifunovic, D. Nuzman, A. Cohen, A. Zaks, and I. Rosen2009 Parallel Architectures and Compilation Techniques (PACT09), Raleigh, North Carolina, September 2009.
Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCsD. Ludovici, A. Strano, G. N. Gaydadjiev, L. Benini, D. Bertozzi2010 Proceedings of Design, Automation and Test in Europe 2010 (DATE), pp. 679-684, Dresden, Germany, March 2010
Achieving High Memory Performance from Heterogeneous Architectures with the SARC Programming ModelRoger Ferrer, Vicenc Beltran, Marc Gonzalez, Xavier Martorell, and Eduard Ayguade200910th Workshop on Memory Performance: Dealing with Applications, systems, and architecture (MEDEA 2009), Proc. of the 10th MEDEA Workshop, ACM, ISBN: 978-1-60558-830-8 , September 2009.
Designing Efficient Processors Using Compiler-Directed OptimisationsTimothy M. Jones, Michael F.P. O'Boyle, Jaume Abella, Antonio González and Oğuz Ergin200711th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT '07)
A Low-Cost Cache Coherence Verification Method for Snooping SystemsD. Borodin, B.H.H. Juurlink200811th Euromicro Conference on Digital System Design (DSD-2008)
Evaluating the Effects of Compiler Optimisations on AVFTimothy M. Jones, Michael F.P. O'Boyle and Oğuz Ergin200812th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT)
An Evaluation of Behaviors of S-NUCA CMPs running scientific workloadP. Foglia, F. Panicucci, C. A. Prete, M. Solinas200912th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD09), August 27-29, Patras, Greece, pp. 26-33, 2009
Re-Nuca: Boosting CMP performances through block replicationP. Foglia, M. Solinas et al:201013th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD2010), September 1-3, Lille, France
Mapping Parallelism to Multi-cores: A Machine Learning Based ApproachZheng Wang and Michael F.P. O'Boyle200914th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)
Congestion Management in MINs through Marked and Validated PacketsJ.L. Ferrer, E. Baydal, A. Robles, P. Lopez, and J. Duato200715th Euromicro International Conference on Parallel, Distributed and Network-Based Processing
Scalability of Macroblock-level parallelism for H.264 decodingMauricio Álvarez, Alex Ramirez, Cor Meenderinck, Ben Juurlink and Mateo Valero200915th International Conference on Parallel and Distributed Systems (ICPADS'09), ISBN: 978-0-7695-3900-3, Shenzhen (China), Dec 2009.
An Extension of the StarSs Programming Model for Platforms with Multiple GPUsEduard Ayguadé, Rosa M. Badia, Francisco D. Igual, Jesús Labarta, Rafael Mayo, and Enrique S. Quintana-Ortí200915th International Euro-Par Conference, pp. 851-862, Delft (Netherlands), Aug 2009.
A Scalable and Early Congestion Management Mechanism for MINsoan-Lluís Ferrer, Elvira Baydal, Antonio Robles, Pedro López, José Duato201018th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP 2010)
Capturing Topology-Level Implications of Link Synthesis Techniques for Nanoscale Networks-on-ChipD. Ludovici, D. Bertozzi, L. Benini, G. N. Gaydadjiev200919th ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 125-128, Boston, USA, May 2009
Publications found: 228 Next page

 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants

IST-FET project funded under the 6th Framework Programme

Design By
Usability Group in Pisa
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