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Scalable computer ARChitecture
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MEDEA Workshop - MEmory performance: DEaling with Applications, systems and architecture (deadline August 7th 2008)

Date:Oct 25, 2008Location: Toronto, Canada
Duration: two days
MEDEA Workshop
held in conjunction with PACT 2008 Conference Oct. 25-29 2008 Toronto, Canada

MEDEA aims to continue the high level of interest of the previous editions held with PACT Conference since 2000. Due to the ever-increasing gap between CPU and memory speed, there is always great interest in evaluating and proposing processor, multiprocessor, CMP, multi-core and system architectures dealing with the "memory wall" and wire-delay problems. At the same time, a modular high-level design is becoming more and more attracting in order to reduce design costs.
MEDEA Workshop wants to continue to be a forum for academic and industrial people to meet, discuss and exchange their ideas and experience in the design and evaluation of architectures for embedded, commercial and general/special purpose systems taking into account memory issues.
Proceedings of the Workshop will be published under ACM ISBN.
As in the previous years, a selection of papers will be considered for publication on transactions on HIPEAC ( The format of the workshop includes the presentation of selected papers and discussion after each presentation.

Topics of interest
  • Memory hierarchy design, analysis, tuning for embedded, general and special purpose systems
  • On-chip Multiprocessors and System On Chip architectures, development tools and applications
  • Issues in memory hierarchy design of scalable single chip systems
  • Memory hierarchy issues for heterogeneous and accelerator-based systems
  • Solutions for embedded, DSP, commercial, scientific and technical workloads
  • Inter-Chip and Intra-Chip memory latency tolerant and reduction techniques
  • Cache coherence and memory models
  • Exploitation of application parallelism (e.g.: ILP, TLP, DLP)
  • Transactional Memory
  • Compile/link time optimization techniques
  • Network On Chip
  • Low-Power/Wire Delay design of memory hierarchies
  • Processor and System Architectures
  • Academic/industrial experience in high performance, embedded systems and memory design

Important dates
  • July 31st, 2008 - Abstract Submission (not mandatory)
  • August, 7th 2008 - Paper Submission Deadline
  • September, 21st 2008 - Acceptance Notification
  • September, 28th 2008 - Final Papers Due
  • 25-26 October 2008 (to be defined) - Workshop will start

Further information

 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants

IST-FET project funded under the 6th Framework Programme

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