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Scalable computer ARChitecture
SARC Project
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Title arrowAuthor(s) Year Where 
A Polymorphic Register File ArchitectureCB Ciobanu, G.K. Kuzmanov, A. Ramirez, G. N. Gaydadjiev2009Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), pp. 245-248, Terrassa, Spain, July 2009
A Scalable and Early Congestion Management Mechanism for MINsoan-Lluís Ferrer, Elvira Baydal, Antonio Robles, Pedro López, José Duato201018th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP 2010)
Instruction-Level Fault Tolerance ConfigurabilityD. Borodin, B.H.H. Juurlink, S. Hamdioui, S. Vassiliadis2008Journal of Signal Processing Systems
Joint Compiler/Hardware Exploration for Fair Comparison of ArchitecturesDesmet, V.; Girbal, S.; Temam, O.2009Proceedings of the 13th Workshop on Interaction between Compilers and Computer Architecture
Proposition for a sequential accelerator in future general-purpose manycore processorsP. MICHAUD, Y. SAZEIDES, A. SEZNEC.2010International Conference on Computing Frontiers
Re-Nuca: Boosting CMP performances through block replicationP. Foglia, M. Solinas et al:201013th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD2010), September 1-3, Lille, France
(When) Will CMPs hit the Power Wall?C.H. Meenderinck, and B.H.H. Juurlink2008Highly Parallel Processing on a Chip (HPPC)
(When) Will CMPs hit the Power Wall?C.H. Meenderinck and B.H.H. Juurlink2008Technical Report
(When) Will CMPs hit the Power Wall?C.H. Meenderinck and B.H.H. Juurlink2007Workshop on Circuits, Systems and Signal Processing (ProRISC)
. Schemes for Avoiding Starvation in Transactional Memory ProtocolsM. M. Waliullah and P. Stenstrom2009Journal of Concurrency and Computation: Practice and Experience, Vol 21, No 7, pp. 859-873, 2009
A 128x128x24Gb/s Crossbar, Interconnecting 128 tiles in a single hop, and Occupying 6% of their areaG. Passas, M. Katevenis, D. Pnevmatikatos20104th ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2010)
A Chip MultiProcessor Accelerator for Video DecodingC.H. Meenderinck, B.H.H. Juurlink2008Workshop on Circuits, Systems and Signal Processing (Prorisc)
A CMP L2 NUCA Cache Power Reduction TechniquePierfrancesco Foglia, Francesco Panicucci, Cosimo A. Prete, Marco Solinas2008IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XI), pp 137-137, Yokohama, Japan, vol. 1
A deterministic, concurrent intermediate representation for portable and scalable performanceC. Miranda, P. Dumont, A. Cohen, M. Duranton, and A. Pop. Erbium2010ACM Intl. Conf. on Computing Frontiers (CF10), May 2010. 2 pages and poster
A Highly Scalable Parallel Implementation of H.264Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink, Andrei Tereckho, Jan Hoogerbrugge, Mauricio Álvarez, Alex Ramirez and Mateo Valero2009Transactions on High-Performance Embedded Architectures and Compilers, vol. 4, no. 2, Sep 2009.
Publications found: 228 Next page

 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants

IST-FET project funded under the 6th Framework Programme

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