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Scalable computer ARChitecture
SARC Project
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6th HiPEAC Industrial Workshop

Date:Nov 26, 2008Location:Thales, France
Duration:1 day
The ubiquity of embedded electronics in all aspects of human life as well as the emerging applications in automotive, aerospace and security industry suggest multi-core architectures as a natural path to scalable performance. Still, such applications have challenging requirements beyond those existing in high performance computing and high volume embedded systems.

Beside the increasing need of performance, low power consumption, and the challenges the industry is facing to effectively program parallel architectures, such specific systems are usually subject to conflicting requirements such as flexibility (or genericity) to compensate for low volume production needs, and customizability to address each application domain needs.

Furthermore, a lot of these systems, especially in the automotive and the aerospace domains, are subject to hard real time and safety critical requirements that reduce the efficiency and potential of current multi-cores and high performance architectures.

The goal of this workshop is to bring together researchers from academia and industry to investigate the challenges, techniques, tools and requirements of multi-core architectures in embedded systems, especially in the automotive, aerospace, and security industry.

The topics of interest include, but are not limited to

Processor customization and application specific architectures

Parallel and multi-core systems for real time and safety critical systems (including performance predictability, reliability constraints, ?).

Low power techniques for multi-cores

Reconfigurable and adaptive architectures

Heterogeneous multi-core architectures and virtualization techniques

Compilers, tools and methods for embedded, high performance and heterogeneous parallel architectures

Mapping parallel applications to heterogeneous multi-cores

Simulation tools, design space exploration and performance modeling of multi-core and/or application specific architectures.

Iterative compilation techniques for embedded and high performance systems Domain/application specific accelerators

Important Dates

Submission deadline October 15th, 2008

Notification of acceptance November 1st, 2008

Workshop November 26th, 2008

For more information, please visit the workshop homepage

 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants

IST-FET project funded under the 6th Framework Programme

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Usability Group in Pisa
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