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Scalable computer ARChitecture
 
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Title Author(s) arrowYear Where 
Compiling Effectively for Cell B.E. with GCC Ira Rosen, Ben Elliston, Revital Eres, Alan Modra, Dorit Nuzman2009CPC 2009, January 7-9, 2009, Zurich, Switzerland
Scheduling and NoC Traffic Reduction in T-SDF Architecture R. Giorgi, N. Puzovic2006ACACES 2006 poster session. L┤Aquila, Italy, July 2006.
Parallel H.264 Decoding on an Embedded Multicore ProcessorA. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, A. Terechko, J. Hoogerbrugge, M. Alvarez, A. Ramirez2009Proc. of Hipeac Conference
Analysis of Video Filtering on the Cell ProcessorA. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, M. Alvarez, A. Ramirez2008Proc. of International Symposium on Circuits and Systems (ISCAS)
Analysis of Video Filtering on the Cell ProcessorA. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, M. Alvarez, A. Ramirez2007Proc. of Prorisc Conference
Analysis of Embedded Video Coder System: a System Level ApproachA. Bardine, A. Bechini, P. Foglia, C. A. Prete2006ACM SIGARCH Computer Architecture News , Vol. 34, Issue1, pp. 71-76, March 2006
Impact of On-Chip Network Parameters on NUCA Cache PerformanceA. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete2009 IET Computers & Digital Techniques, Vol. 3, No. 5, pp. 501-512, August 2009
Way-Adaptable D-Nuca CachesA. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete2010International of High Performance Systems Architecture, to appear
Performance Sensitivity of NUCA Caches to On-Chip Network ParametersA. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C.A. Prete2008Proc. 20th Int. Symp. Computer Architecture and High Performance Computing (SBAC-PAD), pp. 167-174, Campo Grande, Brazil, October 2008
On-Chip Networks: Impact on the Performance of NUCA cachesA. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C.A. Prete2008Proc. of the 11th Euromicro Conference on Digital System Design. WIP session, pp 55-56, Parma (Italy)
NUCA caches: Analysis of Performance Sensitivity to NOC ParametersA. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C.A. Prete2008ACACES 2008 poster session. L┤Aquila, Italy, July 2008
Implementation Issues of Way Adaptable D-NUCA CachesA. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C.A. Prete2008ACACES 2008 poster session. L┤Aquila, Italy, July 2008
Dynamic Optimization Technique for D-NUCA CachesA. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C.A. Prete2008ACACES 2008 poster session. L┤Aquila, Italy, July 2008
Leveraging Data Promotion for Low Power D-NUCA CachesA. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C.A. Prete, P. Stenstr÷m2008Proc. 11th EUROMICRO Conf. Digital System Design, pp. 307-316, Parma, Italy, September 2008
Way Adaptable D-NUCA cachesA. Bardine. P. Foglia, C. A. Prete2006ACACES 2006 poster session. L┤Aquila, Italy, July 2006.
   
Publications found: 228 Next page
   

 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants



IST-FET project funded under the 6th Framework Programme


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