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Scalable computer ARChitecture
 
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MEDEA Workshop - MEmory performance: DEaling with Applications, systems and architecture (deadline July 5 2009)

Date:Sep 13, 2009Location:Raleigh, North Carolina, USA
Duration:1 day
 
Description: 
 
MEDEA Workshop
held in conjunction with PACT 2009 Conference Sep. 12-16 2008 Raleigh, North Carolina, USA

MEDEA aims to continue the high level of interest of the previous editions held with PACT Conference since 2000. Due to the ever-increasing gap between CPU and memory speed, there is always great interest in evaluating and proposing processor, multiprocessor, CMP, multi-core and system architectures dealing with the "memory wall" and wire-delay problems. At the same time, a modular high-level design is b ecoming more and more attracting in order to reduce design costs.
MEDEA Workshop wants to continue to be a forum for academic and industrial people to meet, discuss and exchange their ideas and experience in the design and evaluation of architectures for embedded, commercial and general/special purpose systems taking into account memory issues.

Proceedings of the Workshop will be published under ACM ISBN.
The format of the workshop includes the presentation of selected papers and discussion after each presentation.

Topics of interest

- Memory hierarchy design, analysis and tuning for embedded, general and special purpose systems
- On-chip Multicore and System On Chip architectures, development tools and applications
- Issues in memory hierarchy design of scalable single chip systems
- Memory hierarchy issues for heterogeneous, accelerator-based systems and GPGPUs
- Solutions for embedded, DSP, commercial, scientific and technical workloads
- Inter-Chip and Intra-Chip bandwidth issues and solutions
- Inter-Chip and Intra-Chip memory latency tolerant and reduction techniques
- Coherence, consistency and communication management
- Exploitation of application parallelism (e.g.: ILP, TLP, DLP) related to memory issues
- Compile/link time optimization techniques
- Network On Chip and Photonic Networks
- Low-Power/Wire Delay design of memory hierarchies
- Transactional Memory
- Academic/industrial experience in high performance, embedded systems and memory design

Important dates

June, 28 2009 Abstract Submission (not mandatory)
July, 5 2009 Paper Submission Deadline
August, 7 2009 Acceptance Notification
August, 25 2009 Final Papers Due
September, 13 2009 Workshop will start

Further information

Further information can be found in the Workshop web page


 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants



IST-FET project funded under the 6th Framework Programme


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