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Scalable computer ARChitecture
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5th HiPEAC Industrial Workshop: Tools and Methodology for Parallel Programming

Date:Jun 4, 2008Location:Sant Cugat del Valles, Barcelona, Spain
Duration:1 Day
Organized by: HP Labs, Exascale Computing Lab, Barcelona Research Office Hewlett-Packard, Sant Cugat del Valles, Barcelona, Spain

We live exciting times in the field of parallel architectures. The diminishing IPC returns caused by power and frequency walls have forced a radical change in CPU design. Multicore is here to stay and has become pervasive throughout the computer industry. In high-performance computing, three out of four "TOP 500" systems are clusters of industry-standard multicore nodes. In embedded computing, heterogeneous multicore System-on-Chips have become the dominant standard for high-volume parts.

There is no silver bullet in multicore programming, and formidable computer science problems underlie the programming of this new breed of parallel architectures. Traditional parallel programming paradigms and tools need to be put to the test and questioned. The heterogeneity of cores and accelerators is creating new challenges to the programming models. Locks and multithreading memory semantics are being redefined and transactional programming is on the horizon. With new programming paradigms and a shifting architecture target, new tools and analysis methodologies are also granted.

The goal of this workshop is to bring together researchers from academia and industry to discuss tools and methodologies for analysis, compilation, debugging, verification and simulation of parallel programs. The topics of interest include, but are not limited to:

* Compiler support for explicit parallelism (threads, transactions)
* Tools to aid programmers to identify, exploit, verify, debug, and tune
parallel applications
* Simulation methodology and tools for multicore/manycore/clustered
* Characterization of parallel applications and their scalability
* Reliability and Fault Tolerance for applications running on many-core
and distributed architectures
* I/O issues in parallel computing and parallel applications
* Parallel programming languages, algorithms and applications
* Middleware and run time support for parallelism

Important Dates

Submission deadline April 25th, 2008
Notification of acceptance May 2nd, 2008
Workshop June 4th, 2008


Authors should submit their contributions to Daniel Ortega. Submissions must include a 2-page extended abstract describing the work that is going to be presented. Authors should feel free to present work in progress as well as already published material, and can include related documents with additional details on their research work. Authors should commit to present their research at the workshop in the case it gets selected. Abstract and other workshop material will be made available on the HiPEAC website. The workshop will not publish proceeding.

Further information

Further information may be found in the Workshop web page:

 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants

IST-FET project funded under the 6th Framework Programme

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