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Scalable computer ARChitecture
 
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V.M. Milutinovic: A Solution for the Multiple Writer Problems in shared memory

Date:Nov 20, 2006Location:Pisa, Dept Information engineering
Duration:2 hours
 
Description: 
 
The presentation introduces a series of infinitesimal contributions which (all of them together) may (under specific conditions) reduce the system slow-downs due to resolution of conflicts created by the existence of multiple writers in shared memory multiprocessors. The central contribution is referred to as 'intention to commit', which differs from the Olokotun from Stanford 'two-stage commit' in three ways: (a) Action is done in anticipation (b) Timer is incorporated (c) The approach is built in SMT (Simultaneous MultiThreading). Veljko M. Milutinovic Fellow of the Ieee Department of Computer Engineering, University of Belgrade More information on Prof. Milutinovic on this link More information on the event: foglia@iet.unipi.it


 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants



IST-FET project funded under the 6th Framework Programme


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