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Scalable computer ARChitecture
 
SARC Project
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Title Author(s) Year Where 
On-chip Communication and Synchronization with Cache-Integrated Network InterfacesStamatis Kavadias, Manolis G. H. Katevenis,Michail Zampetakis and Dimitrios S. Nikolopoulos2010Proc. of the 2010 ACM International Conference on Computing Frontiers (CF)
A 128x128x24Gb/s Crossbar, Interconnecting 128 tiles in a single hop, and Occupying 6% of their areaG. Passas, M. Katevenis, D. Pnevmatikatos20104th ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2010)
A Methodology for Facilitating a Fair Comparison of Architecture Research IdeasVeerle Desmet, Sylvain Girbal, Olivier Temam2010IEEE International Symposium on Performance Analysis of Systems and Software
Performance-Effective Operation below Vcc-minNikolas Ladas, Yiannakis Sazeides, Veerle Desmet2010IEEE International Symposium on Performance Analysis of Systems and Software
Software-Based Cache Coherence with Hardware-Assisted Selective Self Invalidations Using Bloom FiltersJ. Ashby, Pedro Diaz, and Marcelo Cintra2010IEEE Transaction on Computer, to appear
V*: A Class of Lazy Versioning HTMs for Low-Cost Integration of Transactional Memory SystemsAnurag Negi, M. M. Waliullah, and Per Stenstrom2010Technical Report, March 2010. Submitted for publication
Characterization and Exploitation of Narrow-Width Loads: The Narrow-Width Cache Approach.Md. Mafijul Islam and Per Stenstrom.2010Technical Report, March 2010. Submitted for publication
Way-Adaptable D-Nuca CachesA. Bardine, M. Comparetti, P. Foglia, G. Gabrielli, C. A. Prete2010International of High Performance Systems Architecture, to appear
Re-Nuca: Boosting CMP performances through block replicationP. Foglia, M. Solinas et al:201013th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools (DSD2010), September 1-3, Lille, France
SAMS Multi-Layout Memory: Providing Multiple Views of Data to Boost SIMD PerformanceC. Gou, G.K. Kuzmanov, G. N. Gaydadjiev201024th International Conference on Supercomputing (ICS'10), Tsukuba, Japan, June 2010 (Best Paper Award)
A deterministic, concurrent intermediate representation for portable and scalable performanceC. Miranda, P. Dumont, A. Cohen, M. Duranton, and A. Pop. Erbium2010ACM Intl. Conf. on Computing Frontiers (CF10), May 2010. 2 pages and poster
The polyhedral model is more widely applicable than you thinkMohamed-Walid Benabderrahmane, Louis-NoŰl Pouchet, Albert Cohen, and CÚdric Bastoul2010Proceedings of the International Conference on Compiler Construction (ETAPS CC10), LNCS, Paphos, Cyprus, March 2010
Design Space Exploration of a Mesochronous Link for Cost-Effective and Flexible GALS NOCsD. Ludovici, A. Strano, G. N. Gaydadjiev, L. Benini, D. Bertozzi2010 Proceedings of Design, Automation and Test in Europe 2010 (DATE), pp. 679-684, Dresden, Germany, March 2010
Parallel H.264 Decoding on an Embedded Multicore ProcessorA. Azevedo, C.H. Meenderinck, B.H.H. Juurlink, A. Terechko, J. Hoogerbrugge, M. Alvarez, A. Ramirez2009Proc. of Hipeac Conference
Introducing hardware TLP support in the Cell processorRoberto Giorgi, Zdravko Popovic, Nikola Puzovic20092009 International Workshop on Multi-Core Computing Systems (MuCoCoS'09), ISBN:978-1-4244-3569-2, Fukuoka, Japan, pp. 657-662
   
Publications found: 228Previous pageNext page
   

 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants



IST-FET project funded under the 6th Framework Programme


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