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Scalable computer ARChitecture
SARC Project
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Title Author(s) Year Where 
Zero Content Augmented CachesJ. Dusser, T. Piquet, A, Seznec2010International Conference on Supercomputing 2009
Proposition for a sequential accelerator in future general-purpose manycore processorsP. MICHAUD, Y. SAZEIDES, A. SEZNEC.2010International Conference on Computing Frontiers
Decoupled Zero-Compressed MemoryJ. Dusser, A, Seznec20104th Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI)
Towards Phase Change Memory as a Secure Main MemoryA. Seznec2010Workshop on the Use of Emerging Storage and Memory Technologies (WEST10)
Phase Change Memory as a Secure Main MemoryA. Seznec2010Computer Architecture Letters
Instruction Precomputation with Memoization for Fault DetectionD. Borodin and B.H.H. (Ben) Juurlink2010DATE-2010: Proceedings of the Design, Automation and Test in Europe
Protective Redundancy Overhead Reduction Using Instruction Vulnerability FactorD. Borodin and B.H.H. (Ben) Juurlink2010Proceedings of the ACM International Conference on Computing Frontiers
Analysis of Task Offloading for AcceleratorsRoger Ferrer, Vicenç Beltran, Marc Gonzàlez, Xavier Martorell and Eduard Ayguadé20105th International Conference, HiPEAC 2010, Pisa, Italy, January 25- 27, 2010, DOI: 10.1007/978-3-642-11515-8_24
Scalability Analysis of Progressive Alignment in a MulticoreSebastián Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramirez and Mateo Valero2010International Wor kshop on Multi-Core Computing Systems (MuCoCoS 2010), Krakow (Poland), Feb 2010.
Evaluation of Parallel H.264 Decoding Strategies for the Cell Broadband EngineC.C. Chi, B.H.H. Juurlink, C.H. Meenderinck2010Proceedings of the International Conference on Supercomputing (ICS)
A Scalable and Early Congestion Management Mechanism for MINsoan-Lluís Ferrer, Elvira Baydal, Antonio Robles, Pedro López, José Duato201018th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP 2010)
A Methodology for the Characterization of Process Variation in NoC LinksC. Hernandez, F. Silla, and J. Duato2010DATE 2010
Improving the Performance of GALS-based NoCs in the Presence of Process VariationC. Hernandez, A. Roca, F. Silla, J. Flich, and J. Duato2010NoCs 2010
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant RoutingS. Rodrigo, J. Flich, A. Roca, S. Medardoni, D. Bertozzi, J. Camacho, F. Silla and J. Duato2010NoCs 2010
Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell ProcessorGeorge Tzenakis, Konstantinos Kapelonis, Michail Alvanos, Konstantinos Koukos, Dimitrios S. Nikolopoulos, and Angelos Bilas2010Proceedings of the Fifth International Conference on High-Performance Embedded Architectures and Compilers (HIPEAC) LNCS Vol. 5952, pages 307--321
Publications found: 228 Next page

 Key Data
  • SARC is an integrated project concerned with long term research in advanced computer architecture
  • Duration: 4 years 
  • Main topic: advanced computer architecture
  • 16 European participants

IST-FET project funded under the 6th Framework Programme

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Usability Group in Pisa
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